(1) Field of the Invention
The present invention relates to a method of fabricating the field programmable gate arrays (FPGAs), and more particularly to the novel antifuse structure of high density and high speed FPGAs.
(2) Description of the Related Art
Gate arrays are largely a matrix of integrated circuit structures, such as logic gates and their associated input and output structures which are isolated from one another. These logic gates are overlaid with vertical and horizontal wiring channels, which interconnect the logic gates and input and output structures in a pattern to perform a user-specified function.
Field programmable gate arrays (FPGAs) offer important improvement in turn around time and eliminate non-recurring engineering cost for application specific integrated circuit (ASIC) prototype compared to traditional mask-programmable gate arrays (MPGAs). In a field programmable gate array, the connections between transistors, logic blocks, and input and output circuits are made by interconnect elements. There are three types of the interconnect elements currently in use. A MOSFET is either on or off depending on the state of an accompanying static random access memory (SRAM) cell. The program information is volatile and must be stored elsewhere and rebooted at power-up. EPROM or flash memory, of course, also controls the MOSFET; it can also serve as the interconnect element itself. An antifuse is made of an insulating layer sandwiched by two electrodes. The interconnect element is normally off until a programming voltage/current pulse breaks down the insulator and turns it into a low-value resistor. Numerous antifuse materials and structures have been employed in the past. For example, see U.S. Pat. No. 5,493,147 to Holzworth et al., U.S. Pat. No. 5,537,056 to McCollum, and U.S. Pat. No. 5,557,136 to Gorden et al. (the entire disclosures of which are herein incorporated by reference). Dielectric based antifuses with Si bottom electrodes and amorphous silicon (.alpha.-Si) dielectric layer with TiW metal top electrodes are now used in FPGAs.
Referring now to FIG. 1, it illustrates a cross sectional view of the conventional antifuse structure. First, a field oxide layer 3 for isolation is formed on a silicon substrate 1. A layer of bottom electrode 5 which is typically made of doped silicon or TiW alloy is formed on the field oxide layer 3. A dielectric layer 7 such as 2000 Angstroms of CVD oxide is formed over bottom electrode and then masked and etched to define an antifuse via opening. Next, a thin dielectric layer 9 such as .alpha.-Si or oxide/nitride/oxide (ONO) is deposited. Finally, a top electrode 11 is formed overlaying the dielectric layer to complete the formation of an antifuse structure of FPGAs.
As the via sizes of the IC devices become smaller, there is always the concern of step coverage problem. The issue of poor step coverage of the dielectric layer creates weak points 13 that affects the reliability of the antifuses. Besides, the non-uniform thicknesses of the dielectric layer and top electrode in the concave area further degrade the performance of the field programmable gate arrays.
To solve the above-mentioned problems, the present invention provides a method of making an antifuse structure of the FPGA device by the assisting of liquid phase deposition (LPD) oxide, which is capable of providing better step coverage in the dielectric layer/ electrodes interfaces of the antifuse structure.
The liquid phase deposition (LPD) is a newly developed technology, which can be used to grow silicon dioxide in an aqueous solution at low temperature. Having the features of selective deposition against photoresist and conformal growth, the silicon dioxide prepared by LPD can be utilized to simplify the antifuse process and improve the uniformity of the dielectric layer. Liquid phase deposition of silicon dioxide is described in the article entitled "A Selective SiO.sub.2 Film-Formation Technology Using Liquid-Phase Deposition for Fully Planarized Multilevel Interconnects," J. Electrochem. Soc., Vol. 140, No. 8, August 1993, which is fully incorporated by reference.
Within the prior art, there are some references addressing different applications of liquid phase oxide deposition. However, none appear to be directed to the specific application of the present invention, namely the use of the phase liquid oxide deposition to simplify the antifuse process in making a FPGA. For example, U.S. Pat. No. 5,470,681 to Brunner et al. provides an improved phase shift mask structure for making lithographic exposures by selective deposition of oxide through openings in a pattern of polyimide or similar organic material. U.S. Pat. No. 5,472,898 to Hong et al. utilizes a silicon dioxide formed by liquid phase deposition in making a mask read only memory (ROM). U.S. Pat. No. 5,472,902 to Lur discloses a method of forming an isolation structure on a silicon substrate having a silicon-on-insulator (SOI) structure.